1. Field of the Invention
The present invention relates to a semiconductor device which has a duty detection circuit that detects a duty error in an internal clock synchronized with an external clock. More particularly, the invention relates to a semiconductor device which has a duty detection circuit capable of performing accurate duty measurement.
Priority is claimed on Japanese Patent Application No. 2009-036509, filed Feb. 19, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
Japanese Unexamined Patent Application, First Publication, No. JP-A-2006-303553 discloses a semiconductor memory device which has a duty detection circuit that detects a duty error in an internal clock synchronized with an external clock.